1. Field of the Invention
The present invention relates to a solid-state image capturing device, a method of manufacturing the solid-state image capturing device, and an image capturing apparatus.
2. Description of the Related Art
With the miniaturization of each pixel of a CMOS image sensor, the area of a pixel transistor with respect to a photodiode in a unit pixel becomes larger.
When a ratio of the area of the pixel transistor in the unit pixel becomes larger, the area of the photodiode becomes smaller. For this reason, a problem with a reduction in sensitivity may arise. As shown in FIG. 13, some (for example, oblique incident light) of light L incident on gate electrodes 120 of the pixel transistor may be reflected or absorbed. Therefore, due to a reduction in light arriving to the photodiode 110, the problem of the deterioration in sensitivity may arise.
Since it is necessary to ensure the area corresponding to an overlapped area of the pixel transistor on an isolation area, a problem may arise in that the area of the photodiode may not be expanded and the number of saturation electrons is reduced.
In recent years, the number of sensitivity electrons and the number of saturation electrons have also been reduced with the reduction in a pixel size. For this reason, a problem may arise in that the output voltage of a signal of a pixel is reduced. Therefore, it is preferable to improve the efficiency (conversion efficiency) of converting electrons to voltage in a pixel. As shown in FIG. 14, however, a problem may arise in that a gate capacity is increased when the overlapped portions of the gate electrodes 120 on the isolation area 130 are large.
When the overlapped portions of the gate electrodes 120 on the isolation area 130 are large even with the miniaturization of the element, the occupation area of a photodiode 110 has to be decreased, thereby resulting in the deterioration in sensitivity.
In order to solve the above-mentioned problems, it is necessary to reduce the overlapped portion of the transistor on the isolation area. However, when the overlapped portions of the gate electrode are reduced, as shown in FIG. 15, for example, a gap 125 may occur in a gate width direction of the gate electrode 120 in a case of the occurrence of a join gap in an exposure device. In this case, when ions are implanted to form source and drain areas 141 and 142, the ions are implanted from the gap 125 to a semiconductor substrate 100 and the source and drain areas 141 and 142 may be formed in a shorted state.
There was suggested a method of manufacturing a gate electrode using a self-alignment technique as a technique capable of solving an overlapped portion of a polysilicon gate in an SRAM or the like (for example, see Japanese Unexamined Patent Application Publication No. 2006-93222). With this manufacturing method, it is difficult to take contacts when a transistor wit with a short gate length (L length) is manufactured with a logic circuit of a peripheral circuit section. Therefore, in a solid-state image capturing element or the like, it is difficult to mount a gate electrode, which has to be formed with a minute pattern, of a peripheral circuit section and a gate electrode of a pixel section together on a chip.